1. Field of the Invention
The present invention relates to communication systems and, more particularly, to circuitry for providing accurate, synchronized timing between a transmitter and receiver of multimedia content.
2. Description of the Related Art
Communication systems that communicate multimedia content, such as audio and video files, are required to utilize accurate timing such that the sequence of events within the multimedia content can be reconstructed at the receiver. To facilitate such timing synchronization certain protocols are applied to the transmission. The source circuitry (the transmitter) utilizes a time stamp flag (TSF) timer and a media access control (MAC) protocol such that a 27 MHz clock can be used in the source circuitry for timing of the transmission without directly encoding the clock into the transmission.
The sink circuitry (the receiver) utilizes the TSF to properly order the multimedia information for display by the receiver. However, the 27 MHz clock that is used in the sink circuitry is not synchronized with the source circuitry 27 MHz clock, i.e., the receiver-transmitter operate as an open-loop system with respect to the 27 MHz clock. As such, any phase shift that occurs between the source and the sink circuitry due to channel dynamics causes a timing error to accumulate between the source and sink circuitry. When the misalignment has a length of approximately a frame of multimedia data, the sink circuitry deletes or drops a frame. In most applications, a single dropped frame to realign the source and sink circuitry is not recognized by a viewer or user of the multimedia data. However, in some situations, a frame drop is recognizable to the viewer and must be avoided.
Therefore, there is a need in the art for circuitry that provides synchronization between the source and sink circuits of a communication system.